D16/M Changes and Revisions.


December 29, 2006:


We now have mass storage!  I have completed an SD Flash Memory Card Interface Module for the D16/M.  It is documented on the Peripherals Page.  I have included a copy of a test program which contains code to read and write SD card sectors.


I have re-organized this Change Page so that the changes and revisions are listed in reverse order; with the most recent developments at the top of the page.


July 2, 2005:


Here it is:  the Indexed Addressing modification is complete!  Just about all of the system documentation has changed to reflect Indexed Addressing and all of the new machine instructions.  I have also re-organized the D16/M Microcode ROM listings so that they are easier to read, with hex representation as well as binary on each page.  Most all of the system photographs are new; you may need to click your browser "refresh" button for them to replace the old ones on your display.


The CPU schematic is now at V. 3.0 (was 2.1).

The Main Memory Module is now at V. 1.2 (was 1.1).

The State Diagrams, Microcode Source Listing, and ROM listing are at V. 2.0 (were 1.1, unmarked).


The new Serial/Parallel I/O Module is also complete, and I have documented it and the Main Memory Module on the new D16/M Peripherals Page.


April 15, 2005:


I have revised the D16_uinstr file, which contained some errors in its description of the operation of the Jump bits.


I have added a new file, D16_uprog_guide.  This is a detailed Microprogramming Guide for the D16/M.  It discusses the operation of the D16 microprogram sequencer in detail, and it supplies additional explanation (beyond that contained in the D16_uinstr file itself) of the "Microprogram Language" that I have used to describe the basic machine micro-operations.


March 27, 2005:


I have revised all of the schematics for the D16/M CPU, front panel, and memory module.  These changes simply clean up the drawings and fix known bugs--see the new Drawing Notes included in each revised schematic for details.


The CPU schematic is now at V. 2.1 (was 2.0).

The Front Panel is now V. 1.1 (was 1.0, mis-marked "00").

Memory Module is now V. 1.1 (was 1.0, mis-marked "00").


Should anyone require the old data for any reason, I am maintaining a History Folder.


The new Serial/Parallel Interface Module is nearing completion; as soon as it is fully debugged, I will post the design information on the TimeFracture Web site.


Big changes are coming!  I have completed the design of the Indexed Addressing modification for the D16/M CPU, and  I hope to implement it within a couple of months.  The Instruction Set will grow from 49 instructions to 73!  As soon is it is complete, this modification will raise the CPU to revision level 3.0.